Memory device with multi-level storage cells and apparatuses, systems and methods including same

ABSTRACT

The present invention comprises memory devices, apparatuses and systems including multiple bit per cell memory cells and methods for operating same. The multiple bit per cell memory cells of the present invention have higher memory densities than conventional single bit per cell memory cells. Additionally, spare states in multiple bit per cell memory devices that remain unmapped to binary data bits may be advantageously used.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation-in-part of application Ser.No. 09/758,476, filed Jan. 11, 2001, pending.

BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to memory devices withstorage cells capable of storing more than one bit of data, i.e., morethan two voltage levels. More particularly, the present invention is amemory device with storage cells capable of storing 1.5 bits of data, orthree voltage levels, and methods using same.

[0003] Most conventional memory devices, including programmableread-only memory (PROM), electrically-erasable PROM (EEPROM), flashEEPROM, random access memory (RAM), static RAM (SRAM), dynamic RAM(DRAM), synchronous DRAM (SDRAM) and the like, are capable of storing asingle bit of data in a single memory cell. The memory cell of aconventional memory device may represent a data bit with a logical stateof true or high voltage in the presence of stored charge in the memorycell. Conversely, the absence of charge may be representative of a databit with a logical state false or low voltage.

[0004] Memory devices with more than one bit of data per cell are alsoknown in the art. For example, U.S. Pat. No. 5,043,940 to Harraridefines multilevel states in a single memory cell in terms of thethreshold voltage V_(t) of a split-channel flash EEPROM memory cell.Harrari discloses using four discrete voltage levels to store two bitsof data per memory cell by applying multiple programming pulses to eachmemory cell. U.S. Pat. No. 5,163,021 to Mehrota et al. also discloses amulti-level memory system wherein each memory cell is capable of fourthreshold voltage levels.

[0005] U.S. Pat. No. 5,566,125 to Fazio et al. discloses a method andcircuitry for storing discrete amounts of charge in a single flashmemory cell. Fazio et al. also discloses programming a flash memory cellto one of at least three amounts of charge, wherein the amount of chargeplaced in the flash memory cell is increased by increasing the voltagelevel of a programming pulse applied to the memory cell.

[0006] U.S. Pat. No. 5,574,879 to Wells et al. discloses addressingmodes for a dynamic single bit per cell to multiple bit per cell memory.Wells et al. also discloses a memory system containing switch controlfor selecting between standard cell addressing modes and multi-levelcell addressing modes. U.S. Pat. No. 5,594,691 to Bashir disclosesaddress transition detection sensing circuitry for flash memory havingmulti-bit cells and methods for using same. U.S. Pat. No. 5,612,912 toGillingham discloses a method of sensing and restoring voltages in amulti-level DRAM cell.

[0007] However, none of these patents appears to disclose memorydevices, apparatuses, systems and methods of using multi-bit memorycells to provide parity bits or methods of storing and retrievingpartial bits of data from a single memory cell. Thus, there exists aneed in the art for memory devices, apparatuses, systems and methods ofusing multi-bit memory cells to provide parity bits in a memory devicebased on multiples of 8 bits.

BRIEF SUMMARY OF THE INVENTION

[0008] The present invention comprises memory devices, apparatuses andsystems including multiple bit per cell memory cells and methods forusing same. The multiple bit per cell memory cells of the presentinvention have higher memory densities than conventional single bit percell memory cells. Additionally, spare states in multiple bit per cellmemory devices that remain unmapped to binary data bits may beadvantageously used for storing information. While multiple bit per cellmemory cells having more than three states are contemplated, a memorycell with three states is preferable to a memory cell with four or morestates because of the added difficulty in distinguishing four or morememory states in a given voltage range versus only three states, i.e.,reliability decreases with narrower voltage margins between cell states.

[0009] An embodiment of a multiple bit per cell memory device inaccordance with the present invention includes a command and addressdecode block connected to a command bus and an address bus, a datainput/output (I/O) block connected to the command and address decodeblock and connected to a data bus, and a memory array of multiple bitmemory cells connected to the command and address decode block and thedata I/O block.

[0010] An embodiment of a memory card in accordance with the presentinvention includes a substrate for mounting and interconnectingintegrated circuits, and at least one multiple bit per cell memorydevice integrated circuit mounted on the substrate, wherein the at leastone multiple bit per cell memory device integrated circuit includes acommand and address decode block connected to a command bus and anaddress bus, a data input/output (I/O) block connected to the commandand address decode block and connected to a data bus, and a memory arrayof multiple bit memory cells connected to the command and address decodeblock and the data I/O block.

[0011] An embodiment of a computer system in accordance with the presentinvention includes an input device, an output device, a processorconnected to the input device and the output device, a memory deviceconnected to the processor device and including at least one multiplebit per cell memory device, wherein each of the at least one multiplebit per cell memory device includes a command and address decode blockconnected to a command bus and an address bus, a data input/output (I/O)block connected to the command and address decode block and connected toa data bus, and a memory array of multiple bit memory cells connected tothe command and address decode block and the data I/O block.

[0012] An embodiment of a semiconductor substrate in accordance with thepresent invention includes at least one multiple bit per cell memorydevice mounted on the substrate, wherein the at least one multiple bitper cell memory device includes a command and address decode blockconnected to a command bus and an address bus, a data input/output (I/O)block connected to the command and address decode block and connected toa data bus, and a memory array of multiple bit memory cells connected tothe command and address decode block and the data I/O block.

[0013] A method embodiment for mapping states of a multiple bit per cellmemory device to binary data bits is disclosed. Method embodiments foroperating a multiple bit per cell memory device are also disclosed.

[0014] These devices, apparatuses, systems and methods and attendantadvantages of the present invention will be readily understood byreading the following detailed description in conjunction with theaccompanying figures of the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0015] In the drawings, which illustrate what is currently regarded asthe best mode for carrying out the invention and in which like referencenumerals refer to like parts in different views or embodiments:

[0016]FIG. 1 is a voltage diagram of an embodiment of a multiple bitmemory cell in accordance with the present invention.

[0017]FIG. 2 is a block diagram of a multiple bit per cell memory devicein accordance with the present invention.

[0018]FIG. 3 is a block diagram of a memory card including at least onemultiple bit per cell memory device of the present invention.

[0019]FIG. 4 is a block diagram of a computer system including themultiple bit per cell memory device of the present invention.

[0020]FIG. 5 is a plan view of a semiconductor substrate including atleast one integrated circuit die having at least one multiple bit percell memory device in accordance with the present invention.

[0021]FIG. 6 is a flow chart of a method of mapping the unique states ofa multiple bit per cell memory cell to unique states of binary data bitsand assigning spare states for erased, default or invalid data states.

[0022]FIG. 7 is a flow chart of a method of operating a multiple bit percell memory device in accordance with the invention.

[0023]FIG. 8 is a flow chart of a method of erasing data in a multiplebit per cell memory device in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] U.S. Pat. Nos. 5,566,125 to Fazio et al., 5,574,879 to Wells etal., 5,594,691 to Bashir and 5,612,912 to Gillingham are each expresslyincorporated herein by reference for all purposes. The primary advantageof the multiple bit per cell memory cells disclosed herein is greatermemory density relative to conventional single bit per cell memory cellsor, alternatively, reduced semiconductor die real estate relative toconventional single bit per cell memory cells.

[0025]FIG. 1 is a voltage diagram of an embodiment of a multiple bitmemory cell in accordance with the present invention. In particular,FIG. 1 illustrates a 1.5 bit memory cell 100 in accordance with thepresent invention. The 1.5 bit memory cell 100 includes three states, 0,1 and 2, corresponding roughly to the voltage regions between a powersource, V_(CC), and ground potential, GND, as indicated. The threestates are separated by two reference voltages, V_(R1) and V_(R2).Memory devices including memory cells with 2 bits per cell (or fourstates) in Flash EEPROM and DRAM technologies and methods formanufacturing same are known in the art. For this reason, further detailregarding the storage of more than two states in a memory cell will notbe included herein.

[0026] Table 1 below, is an exemplary mapping of two 1.5 bit memorycells, CELL0-CELL1, each with three states, to three binary bits,BIT0-BIT2. In order to retrieve data from a cell which stores a fractionof a data bit, it is necessary to read at least two cells. The ninepossible states of the two cells are mapped into eight data statesrepresenting three binary data bits, and one spare state. The ninthstate, State 8, is a spare state. The spare state may be used as anerased or unwritten state, or as an error state (data is invalid). Ascan be seen from Table 1 below, the mapping of two 1.5 bit memory cells,CELL0-CELL 1, each with three states to three binary bits, BIT0-BIT1, isa mapping of base 3 numbers (two 1.5 bit cells each cell having threestates) to base 2 numbers (three binary bits), each unique mappingrepresenting a state. TABLE 1 State CELL0 CELL1 BIT2 BIT1 BIT0 0 0 0 0 00 1 0 1 0 0 1 2 0 2 0 1 0 3 1 0 0 1 1 4 1 1 1 0 0 5 1 2 1 0 1 6 2 0 1 10 7 2 1 1 1 1 8 2 2 X X X

[0027] The example mapping shown in Table 1, above, may be extended toany number of cells. Table 2, at the end of this specification, is atable illustrating one possible mapping of six 1.5 bit memory cells,C0-5, to nine binary data bits, B0-8. The left-most column of the tablein Table 2, is the state column with a unique number of each of the 729possible states in a group of six, 3-state memory cells. The six 1.5 bitmemory cells are referred to herein as a “group of 1.5 bit memory cells”or alternatively as a “group of 3-state memory cells.” The nine binarydata bits, B0-8, mapped from the group of 1.5 bit memory cells may bearranged as eight data bits and one parity bit. Note that there areextra or “spare states,” specifically, states 512-728, denoted by an “X”in the bit columns, B0-8. These 217 spare states may be powered up in aninvalid data state, or may be erased into the invalid data state. Groupsof 1.5 bit memory cells may be arranged in any suitable topology to formmultiple bit per cell memory devices. Thus, Table 2, like Table 1, is amapping of base 3 numbers (six 1.5 bit cells each cell having 3 states)to base 2 numbers (nine binary data bits).

[0028]FIG. 2 is a block diagram of a multiple bit per cell memory device200 in accordance with the present invention. The multiple bit per cellmemory device 200 includes a command and address decode block 202connected to a data input/output (I/O) block 204, and a memory array 206connected to both the command and address decode block 202 and the dataI/O block 204. The command and address decode block 202 may be connectedexternally to a command bus and to an address bus. The data I/O block204 may be connected externally to a bidirectional data bus. The memoryarray 206 further includes at least one group 208 of multiple bit percell memory cells 210 and a parity generator 212. Although only onegroup 208 and one multiple bit per cell memory cell 210 are shown, oneof ordinary skill in the art will recognize that the group 208 andmultiple bit per cell memory cell 210 may be arranged and scaled toaccommodate virtually any configuration of memory array. The paritygenerator 212 allows on-chip parity generation and checking for anymemory states within the multiple bit per cell memory cells 210 that areinvalid data states. Parity generator 212 may also include circuitry forgenerating error-correcting codes, applying the generatederror-correcting codes, detecting errors and correcting errors detected.

[0029] Multiple bit per cell memory cell 210 may be a 1.5 bit per cellmemory cell as depicted in FIG. 1. A group 208 may contain any number ofmultiple bit per cell memory cells 210. Advantageously, group 208 mayinclude six 1.5 bit per cell memory cells mapped to eight data bits andone parity bit as illustrated in Table 2.

[0030] Other multiple bit per cell memory cells are within the scope ofthe present invention, for example, and not by way of limitation, a fivestate, 2.5 bit per cell memory cell. The more states per memory cell,the greater the memory density of the memory device. However, as notedabove, for a given rail-to-rail voltage differential (i.e., groundpotential, GND, to supply voltage, V_(CC)), a three-state memory cell iseasier to reliably manufacture than a memory cell with four or morestates because the voltage thresholds that separate the various statesare wider for a three-state memory cell than for higher-state memorycells.

[0031] The multiple bit per cell memory cell 210 of the presentinvention may be used in conventional memory device architectures suchas dynamic random access memory (DRAM), synchronous DRAM (SDRAM), doubledata rate SDRAM (DDR SDRAM), RAMBUS® DRAM (RDRAM®), extended data-outDRAM,(EDO DRAM), fast-page-mode DRAM (FPM DRAM), static random accessmemory (SRAM), SyncBurst™ SRAM, Zero Bus Turnaround™ SRAM (ZBT™ SRAM),Quad Data Rate™ SRAM (QDR™ SRAM), DDR synchronous SRAM (DDR SRAM) andnonvolatile electrically block-erasable programmable read only memory(Flash).

[0032]FIG. 3 is a block diagram of a memory card 300 including at leastone multiple bit per cell memory device 200 of the present invention.The term “memory card” is synonymous with “memory circuit card” or“memory module” as known to one of ordinary skill in the art. The memorycard 300 of FIG. 3 is shown with a substrate 302 and five multiple bitper cell memory devices 200. However, any number of multiple bit percell memory devices 200 may be included on a given memory card 300.Memory card 300 also includes an interface to external devices. FIG. 3illustrates a system bus interface; however, a memory bus or otherdedicated electrical bus interface is also contemplated within the scopeof the invention. Substrate 302 may be a circuit card or other substratefor mounting integrated circuits.

[0033] The memory card 300 may be configured for compatibility withconventional memory module architectures, for example and not by way oflimitation, single in-line memory module (SIMM), RAMBUS® in-line memorymodule (RIMM™), dual in-line memory module (DIMM), accelerated graphicsport (AGP) in-line memory module (AIMM), and small-outline DIMM(SODIMM).

[0034]FIG. 4 is a block diagram of a computer system 400 including themultiple bit per cell memory device 200 of the present invention.Computer system 400 includes an input device 402, an output device 404,a processor device 406 connected to the input device 402 and the outputdevice 404, and a memory device 408 connected to the processor device.Input device 402 may be a keyboard, mouse, joystick or other computerinput device. Output device 404 may be a monitor, printer or storagedevice, such as a disk drive. Processor device 406 may be amicroprocessor or a circuit card including hardware for processingcomputer instructions.

[0035] Memory device 408 includes at least one multiple bit per cellmemory device 200 in accordance with the present invention. Memorydevice 408 may be a memory card 300 as described above and shown in FIG.3.

[0036]FIG. 5 is a plan view of a semiconductor substrate 500 includingat least one integrated circuit die 502 having at least one multiple bitper cell memory device 200 in accordance with the present invention.

[0037] The semiconductor technology employed is not a limiting factor inthe application of the multiple bit per cell memory device of thepresent invention. While silicon is the preferred bulk semiconductormaterial for commercial electronic devices, gallium arsenide and indiumphosphide substrates may also be employed. Of course, it will beunderstood that the multiple bit per cell memory device of the presentinvention may be fabricated on other semiconductor substrates as well,including, for example, silicon-on-glass (SOG) substrates,silicon-on-insulator (SOI) substrates, and silicon-on-sapphire (SOS)substrates.

[0038]FIG. 6 is a flow chart of a method 600 for mapping the uniquestates of a multiple bit per cell memory cell to unique states of binarydata bits and assigning spare states as invalid data states inaccordance with the present invention. The method 600 includes providing602 a memory device with x memory cells, each with y states, assigning604 a unique state to each of the y^(x) possible states of the memorydevice, mapping 606 each unique state to a unique binary state of nbinary bits, where 2^(n)<y^(x) and n is an integer, and designating 608the y^(x)−2^(n) spare states as invalid data states. As an example ofthe above method, refer again to Table 2. For a multiple bit per cellmemory device with 6 cells (x=6), each memory cell with 3 states (y=3),there are 3⁶=729 unique states (y^(x)). To satisfy the inequality,2^(n)<y^(x), for the largest integer n, select n=9 (i.e., 512<729). Theremaining y^(x)−2^(n) or 729−512=217 spare states may be designated aserased, default, or invalid data states.

[0039]FIG. 7 is a flow chart of a method 700 of operating a multiple bitper cell memory device in accordance with the present invention. Themethod 700 includes providing 702 a multiple bit per cell memory devicewith x memory cells, each with y states, where y>2, applying power 704to the multiple bit per cell memory device, running 706 a self-test oneach of y^(x) possible states of the memory device to identify z faultystates, where z≧0, assigning 708 a unique state to each of the y^(x)−zworking states of the memory device, mapping 710 each assigned uniquestate to a unique binary state of n binary bits, where 2^(n)<y^(x) and nis an integer, and designating 712 the y^(x)−z−2^(n) spare states forerased, default, or invalid data states.

[0040]FIG. 8 is a flow chart of a method 800 of erasing data in amultiple bit per cell memory device in accordance with the presentinvention. Method 800 includes providing 802 a multiple bit per cellmemory device with x multiple bit per cell memory cells, each with ystates, assigning 804 a unique state to each of y^(x) possible states ofthe multiple bit per cell memory device, mapping 806 each assignedunique state to a unique binary state of n binary bits, where2^(n)<y^(x) and n is an integer, utilizing 808 at least one ofy^(x)−2^(n) spare states for indicating erased memory cells, reading 810each of the indicated erased memory cells to determine whether it iserased or not erased, and erasing 812 each of the indicated erasedmemory cells only if it is not erased. TABLE 2 STATE C5 C4 C3 C2 C1 C0B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 10 0 0 0 0 0 0 0 1 2 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 3 0 0 0 0 1 0 0 0 0 00 0 0 1 1 4 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 5 0 0 0 0 1 2 0 0 0 0 0 0 1 01 6 0 0 0 0 2 0 0 0 0 0 0 0 1 1 0 7 0 0 0 0 2 1 0 0 0 0 0 0 1 1 1 8 0 00 0 2 2 0 0 0 0 0 1 0 0 0 9 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 10 0 0 0 1 0 10 0 0 0 0 1 0 1 0 11 0 0 0 1 0 2 0 0 0 0 0 1 0 1 1 12 0 0 0 1 1 0 0 0 00 0 1 1 0 0 13 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 14 0 0 0 1 1 2 0 0 0 0 0 11 1 0 15 0 0 0 1 2 0 0 0 0 0 0 1 1 1 1 16 0 0 0 1 2 1 0 0 0 0 1 0 0 0 017 0 0 0 1 2 2 0 0 0 0 1 0 0 0 1 18 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 19 0 00 2 0 1 0 0 0 0 1 0 0 1 1 20 0 0 0 2 0 2 0 0 0 0 1 0 1 0 0 21 0 0 0 2 10 0 0 0 0 1 0 1 0 1 22 0 0 0 2 1 1 0 0 0 0 1 0 1 1 0 23 0 0 0 2 1 2 0 00 0 1 0 1 1 1 24 0 0 0 2 2 0 0 0 0 0 1 1 0 0 0 25 0 0 0 2 2 1 0 0 0 0 11 0 0 1 26 0 0 0 2 2 2 0 0 0 0 1 1 0 1 0 27 0 0 1 0 0 0 0 0 0 0 1 1 0 11 28 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 29 0 0 1 0 0 2 0 0 0 0 1 1 1 0 1 30 00 1 0 1 0 0 0 0 0 1 1 1 1 0 31 0 0 1 0 1 1 0 0 0 0 1 1 1 1 1 32 0 0 1 01 2 0 0 0 1 0 0 0 0 0 33 0 0 1 0 2 0 0 0 0 1 0 0 0 0 1 34 0 0 1 0 2 1 00 0 1 0 0 0 1 0 35 0 0 1 0 2 2 0 0 0 1 0 0 0 1 1 36 0 0 1 1 0 0 0 0 0 10 0 1 0 0 37 0 0 1 1 0 1 0 0 0 1 0 0 1 0 1 38 0 0 1 1 0 2 0 0 0 1 0 0 11 0 39 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 40 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 410 0 1 1 1 2 0 0 0 1 0 1 0 0 1 42 0 0 1 1 2 0 0 0 0 1 0 1 0 1 0 43 0 0 11 2 1 0 0 0 1 0 1 0 1 1 44 0 0 1 1 2 2 0 0 0 1 0 1 1 0 0 45 0 0 1 2 0 00 0 0 1 0 1 1 0 1 46 0 0 1 2 0 1 0 0 0 1 0 1 1 1 0 47 0 0 1 2 0 2 0 0 01 0 1 1 1 1 48 0 0 1 2 1 0 0 0 0 1 1 0 0 0 0 49 0 0 1 2 1 1 0 0 0 1 1 00 0 1 50 0 0 1 2 1 2 0 0 0 1 1 0 0 1 0 51 0 0 1 2 2 0 0 0 0 1 1 0 0 1 152 0 0 1 2 2 1 0 0 0 1 1 0 1 0 0 53 0 0 1 2 2 2 0 0 0 1 1 0 1 0 1 54 0 02 0 0 0 0 0 0 1 1 0 1 1 0 55 0 0 2 0 0 1 0 0 0 1 1 0 1 1 1 56 0 0 2 0 02 0 0 0 1 1 1 0 0 0 57 0 0 2 0 1 0 0 0 0 1 1 1 0 0 1 58 0 0 2 0 1 1 0 00 1 1 1 0 1 0 59 0 0 2 0 1 2 0 0 0 1 1 1 0 1 1 60 0 0 2 0 2 0 0 0 0 1 11 1 0 0 61 0 0 2 0 2 1 0 0 0 1 1 1 1 0 1 62 0 0 2 0 2 2 0 0 0 1 1 1 1 10 63 0 0 2 1 0 0 0 0 0 1 1 1 1 1 1 64 0 0 2 1 0 1 0 0 1 0 0 0 0 0 0 65 00 2 1 0 2 0 0 1 0 0 0 0 0 1 66 0 0 2 1 1 0 0 0 1 0 0 0 0 1 0 67 0 0 2 11 1 0 0 1 0 0 0 0 1 1 68 0 0 2 1 1 2 0 0 1 0 0 0 1 0 0 69 0 0 2 1 2 0 00 1 0 0 0 1 0 1 70 0 0 2 1 2 1 0 0 1 0 0 0 1 1 0 71 0 0 2 1 2 2 0 0 1 00 0 1 1 1 72 0 0 2 2 0 0 0 0 1 0 0 1 0 0 0 73 0 0 2 2 0 1 0 0 1 0 0 1 00 1 74 0 0 2 2 0 2 0 0 1 0 0 1 0 1 0 75 0 0 2 2 1 0 0 0 1 0 0 1 0 1 1 760 0 2 2 1 1 0 0 1 0 0 1 1 0 0 77 0 0 2 2 1 2 0 0 1 0 0 1 1 0 1 78 0 0 22 2 0 0 0 1 0 0 1 1 1 0 79 0 0 2 2 2 1 0 0 1 0 0 1 1 1 1 80 0 0 2 2 2 20 0 1 0 1 0 0 0 0 81 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 82 0 1 0 0 0 1 0 0 10 1 0 0 1 0 83 0 1 0 0 0 2 0 0 1 0 1 0 0 1 1 84 0 1 0 0 1 0 0 0 1 0 1 01 0 0 85 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 86 0 1 0 0 1 2 0 0 1 0 1 0 1 1 087 0 1 0 0 2 0 0 0 1 0 1 0 1 1 1 88 0 1 0 0 2 1 0 0 1 0 1 1 0 0 0 89 0 10 0 2 2 0 0 1 0 1 1 0 0 1 90 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 91 0 1 0 1 01 0 0 1 0 1 1 0 1 1 92 0 1 0 1 0 2 0 0 1 0 1 1 1 0 0 93 0 1 0 1 1 0 0 01 0 1 1 1 0 1 94 0 1 0 1 1 1 0 0 1 0 1 1 1 1 0 95 0 1 0 1 1 2 0 0 1 0 11 1 1 1 96 0 1 0 1 2 0 0 0 1 1 0 0 0 0 0 97 0 1 0 1 2 1 0 0 1 1 0 0 0 01 98 0 1 0 1 2 2 0 0 1 1 0 0 0 1 0 99 0 1 0 2 0 0 0 0 1 1 0 0 0 1 1 1000 1 0 2 0 1 0 0 1 1 0 0 1 0 0 101 0 1 0 2 0 2 0 0 1 1 0 0 1 0 1 102 0 10 2 1 0 0 0 1 1 0 0 1 1 0 103 0 1 0 2 1 1 0 0 1 1 0 0 1 1 1 104 0 1 0 21 2 0 0 1 1 0 1 0 0 0 105 0 1 0 2 2 0 0 0 1 1 0 1 0 0 1 106 0 1 0 2 2 10 0 1 1 0 1 0 1 0 107 0 1 0 2 2 2 0 0 1 1 0 1 0 1 1 108 0 1 1 0 0 0 0 01 1 0 1 1 0 0 109 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 110 0 1 1 0 0 2 0 0 1 10 1 1 1 0 111 0 1 1 0 1 0 0 0 1 1 0 1 1 1 1 112 0 1 1 0 1 1 0 0 1 1 1 00 0 0 113 0 1 1 0 1 2 0 0 1 1 1 0 0 0 1 114 0 1 1 0 2 0 0 0 1 1 1 0 0 10 115 0 1 1 0 2 1 0 0 1 1 1 0 0 1 1 116 0 1 1 0 2 2 0 0 1 1 1 0 1 0 0117 0 1 1 1 0 0 0 0 1 1 1 0 1 0 1 118 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1190 1 1 1 0 2 0 0 1 1 1 0 1 1 1 120 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 121 0 11 1 1 1 0 0 1 1 1 1 0 0 1 122 0 1 1 1 1 2 0 0 1 1 1 1 0 1 0 123 0 1 1 12 0 0 0 1 1 1 1 0 1 1 124 0 1 1 1 2 1 0 0 1 1 1 1 1 0 0 125 0 1 1 1 2 20 0 1 1 1 1 1 0 1 156 0 1 1 2 0 0 0 0 1 1 1 1 1 1 0 127 0 1 1 2 0 1 0 01 1 1 1 1 1 1 128 0 1 1 2 0 2 0 1 0 0 0 0 0 0 0 129 0 1 1 2 1 0 0 1 0 00 0 0 0 1 130 0 1 1 2 1 1 0 1 0 0 0 0 0 1 0 131 0 1 1 2 1 2 0 1 0 0 0 00 1 1 132 0 1 1 2 2 0 0 1 0 0 0 0 1 0 0 133 0 1 1 2 2 1 0 1 0 0 0 0 1 01 134 0 1 1 2 2 2 0 1 0 0 0 0 1 1 0 135 0 1 2 0 0 0 0 1 0 0 0 0 1 1 1136 0 1 2 0 0 1 0 1 0 0 0 1 0 0 0 137 0 1 2 0 0 2 0 1 0 0 0 1 0 0 1 1380 1 2 0 1 0 0 1 0 0 0 1 0 1 0 139 0 1 2 0 1 1 0 1 0 0 0 1 0 1 1 140 0 12 0 1 2 0 1 0 0 0 1 1 0 0 141 0 1 2 0 2 0 0 1 0 0 0 1 1 0 1 142 0 1 2 02 1 0 1 0 0 0 1 1 1 0 143 0 1 2 0 2 2 0 1 0 0 0 1 1 1 1 144 0 1 2 1 0 00 1 0 0 1 0 0 0 0 145 0 1 2 1 0 1 0 1 0 0 1 0 0 0 1 146 0 1 2 1 0 2 0 10 0 1 0 0 1 0 147 0 1 2 1 1 0 0 1 0 0 1 0 0 1 1 148 0 1 2 1 1 1 0 1 0 01 0 1 0 0 149 0 1 2 1 1 2 0 1 0 0 1 0 1 0 1 150 0 1 2 1 2 0 0 1 0 0 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X X X 658 2 2 0 1 0 1 X X X X X X X X X 659 2 2 0 1 0 2 X XX X X X X X X 660 2 2 0 1 1 0 X X X X X X X X X 661 2 2 0 1 1 1 X X X XX X X X X 662 2 2 0 1 1 2 X X X X X X X X X 663 2 2 0 1 2 0 X X X X X XX X X 664 2 2 0 1 2 1 X X X X X X X X X 665 2 2 0 1 2 2 X X X X X X X XX 666 2 2 0 2 0 0 X X X X X X X X X 667 2 2 0 2 0 1 X X X X X X X X X668 2 2 0 2 0 2 X X X X X X X X X 669 2 2 0 2 1 0 X X X X X X X X X 6702 2 0 2 1 1 X X X X X X X X X 671 2 2 0 2 1 2 X X X X X X X X X 672 2 20 2 2 0 X X X X X X X X X 673 2 2 0 2 2 1 X X X X X X X X X 674 2 2 0 22 2 X X X X X X X X X 675 2 2 1 0 0 0 X X X X X X X X X 676 2 2 1 0 0 1X X X X X X X X X 677 2 2 1 0 0 2 X X X X X X X X X 678 2 2 1 0 1 0 X XX X X X X X X 679 2 2 1 0 1 1 X X X X X X X X X 680 2 2 1 0 1 2 X X X XX X X X X 681 2 2 1 0 2 0 X X X X X X X X X 682 2 2 1 0 2 1 X X X X X XX X X 683 2 2 1 0 2 2 X X X X X X X X X 684 2 2 1 1 0 0 X X X X X X X XX 685 2 2 1 1 0 1 X X X X X X X X X 686 2 2 1 1 0 2 X X X X X X X X X687 2 2 1 1 1 0 X X X X X X X X X 688 2 2 1 1 1 1 X X X X X X X X X 6892 2 1 1 1 2 X X X X X X X X X 690 2 2 1 1 2 0 X X X X X X X X X 691 2 21 1 2 1 X X X X X X X X X 692 2 2 1 1 2 2 X X X X X X X X X 693 2 2 1 20 0 X X X X X X X X X 694 2 2 1 2 0 1 X X X X X X X X X 695 2 2 1 2 0 2X X X X X X X X X 696 2 2 1 2 1 0 X X X X X X X X X 697 2 2 1 2 1 1 X XX X X X X X X 698 2 2 1 2 1 2 X X X X X X X X X 699 2 2 1 2 2 0 X X X XX X X X X 700 2 2 1 2 2 1 X X X X X X X X X 701 2 2 1 2 2 2 X X X X X XX X X 702 2 2 2 0 0 0 X X X X X X X X X 703 2 2 2 0 0 1 X X X X X X X XX 704 2 2 2 0 0 2 X X X X X X X X X 705 2 2 2 0 1 0 X X X X X X X X X706 2 2 2 0 1 1 X X X X X X X X X 707 2 2 2 0 1 2 X X X X X X X X X 7082 2 2 0 2 0 X X X X X X X X X 709 2 2 2 0 2 1 X X X X X X X X X 710 2 22 0 2 2 X X X X X X X X X 711 2 2 2 1 0 0 X X X X X X X X X 712 2 2 2 10 1 X X X X X X X X X 713 2 2 2 1 0 2 X X X X X X X X X 714 2 2 2 1 1 0X X X X X X X X X 715 2 2 2 1 1 1 X X X X X X X X X 716 2 2 2 1 1 2 X XX X X X X X X 717 2 2 2 1 2 0 X X X X X X X X X 718 2 2 2 1 2 1 X X X XX X X X X 719 2 2 2 1 2 2 X X X X X X X X X 720 2 2 2 2 0 0 X X X X X XX X X 721 2 2 2 2 0 1 X X X X X X X X X 722 2 2 2 2 0 2 X X X X X X X XX 723 2 2 2 2 1 0 X X X X X X X X X 724 2 2 2 2 1 1 X X X X X X X X X725 2 2 2 2 1 2 X X X X X X X X X 726 2 2 2 2 2 0 X X X X X X X X X 7272 2 2 2 2 1 X X X X X X X X X 728 2 2 2 2 2 2 X X X X X X X X X

[0041] Although this invention has been described with reference toparticular embodiments, the invention is not limited to these describedembodiments. Rather, the invention is limited only by the appendedclaims, which include within their scope all equivalent devices ormethods that operate according to the principles of the invention asdescribed herein.

What is claimed is:
 1. A multiple bit per cell memory device comprising:a command and address decode block connected to a command bus and anaddress bus; a data input/output (I/O) block connected to said commandand address decode block and connected to a data bus; and a memory arrayof multiple bit memory cells connected to said command and addressdecode block and said data I/O block, wherein information states of saidmultiple bit memory cells are mapped to a plurality of data bits andremaining states of said multiple bit memory cells are configured asinvalid data states.
 2. The multiple bit per cell memory device of claim1, wherein each multiple bit memory cell includes three states or 1.5bits per memory cell.
 3. The multiple bit per cell memory device ofclaim 2, wherein said memory array further comprises a plurality ofgroups of 1.5 bit memory cells.
 4. The multiple bit per cell memorydevice of claim 3, wherein each group of said plurality of groups of 1.5bit memory cells comprises six 1.5 bit memory cells.
 5. The multiple bitper cell memory device of claim 4, wherein each said group of six 1.5bit memory cells is configured for 729 states.
 6. The multiple bit percell memory device of claim 5, wherein said 729 states comprise 8 binarydata bits, 1 binary parity bit, and 217 invalid data states.
 7. Themultiple bit per cell memory device of claim 1, wherein said informationstates are configured to be powered up with invalid data states.
 8. Themultiple bit per cell memory device of claim 1, wherein said memorydevice is configured for operation as a memory device selected from thegroup including dynamic random access memory (DRAM), synchronous DRAM(SDRAM), double data rate SDRAM (DDR SDRAM), RAMBUS® DRAM (RDRAM®),extended data-out DRAM (EDO DRAM), fast-page-mode DRAM (FPM DRAM),static random access memory (SRAM), SyncBurst™ SRAM, Zero BusTurnaround™ SRAM (ZBT™ SRAM), Quad Data Rate™ SRAM (QDR™ SRAM), DDRsynchronous SRAM (DDR SRAM) and nonvolatile electrically block-erasableprogrammable read only memory (Flash).
 9. A memory card comprising: asubstrate for mounting and interconnecting integrated circuits; and atleast one multiple bit per cell memory device integrated circuit mountedon said substrate, said at least one multiple bit per cell memory deviceintegrated circuit comprising: a command and address decode blockconnected to a command bus and an address bus; a data input/output (I/O)block connected to said command and address decode block and connectedto a data bus; and a memory array of multiple bit memory cells connectedto said command and address decode block and said data I/O block,wherein information states of said multiple bit memory cells are mappedto a plurality of data bits and remaining states of said multiple bitmemory cells are configured as invalid data states.
 10. The memory cardof claim 9, further comprising an electrical interface configured forconnection to external circuitry.
 11. The memory card of claim 9,wherein said memory card is configured to be compatible with a memorymodule selected from the group including single in-line memory module(SIMM), RAMBUS® in-line memory module (RIMM™), dual in-line memorymodule (DIMM), accelerated graphics port (AGP) in-line memory module(AIMM), and small-outline DIMM (SODIMM).
 12. The memory card of claim 9,wherein each of said at least one multiple bit memory cell includesthree states or 1.5 bits per memory cell.
 13. The memory card of claim9, wherein said memory array further comprises a plurality of groups of1.5 bit memory cells.
 14. The memory card of claim 13, wherein eachgroup of said plurality of groups of 1.5 bit memory cells comprises six1.5 bit memory cells.
 15. The memory card of claim 14, wherein each saidgroup of six 1.5 bit memory cells is configured for 729 states.
 16. Thememory card of claim 15, wherein said 729 states comprise 8 binary databits, 1 binary parity bit, and 217 invalid data states.
 17. The memorycard of claim 9, wherein said information states are configured to bepowered up in invalid data states.
 18. A computer system comprising: aninput device; an output device; a processor connected to said inputdevice and said output device; a memory device connected to saidprocessor device and including at least one multiple bit per cell memorydevice, each said at least one multiple bit per cell memory devicecomprising: a command and address decode block connected to a commandbus and an address bus; a data input/output (I/O) block connected tosaid command and address decode block and connected to a data bus; and amemory array of multiple bit memory cells connected to said command andaddress decode block and said data I/O block, wherein information statesof said multiple bit memory cells are mapped to a plurality of data bitsand remaining states of said multiple bit memory cells are configured asinvalid data states.
 19. The computer system of claim 18, wherein saidmemory device is further configured to be compatible with a memorymodule selected from the group including single in-line memory module(SIMM), RAMBUS® in-line memory module (RIMM™), dual in-line memorymodule (DIMM), accelerated graphics port (AGP) in-line memory module(AIMM), and small-outline DIMM (SODIMM).
 20. The computer system ofclaim 18, wherein each said at least one multiple bit memory cellincludes three states or 1.5 bits per memory cell.
 21. The computersystem of claim 18, wherein said memory array further comprises aplurality of groups of 1.5 bit memory cells.
 22. The computer system ofclaim 21, wherein each group of said plurality of groups of 1.5 bitmemory cells comprises six 1.5 bit memory cells.
 23. The computer systemof claim 22, wherein each said group of six 1.5 bit memory cells isconfigured for 729 states.
 24. The computer system of claim 23, whereinsaid 729 states comprises 8 binary data bits, 1 binary parity bit, and217 invalid data states.
 25. The computer system of claim 18, whereinsaid information states are configured to be powered up in invalid datastates.
 26. A semiconductor substrate comprising: at least one multiplebit per cell memory device mounted on said substrate, said at least onemultiple bit per cell memory device comprising: a command and addressdecode block connected to a command bus and an address bus; a datainput/output (I/O) block connected to said command and address decodeblock and connected to a data bus; and a memory array of multiple bitmemory cells connected to said command and address decode block and saiddata I/O block, wherein information states of said multiple bit memorycells are mapped to a plurality of data bits and remaining states ofsaid multiple bit memory cells are configured as invalid data states.27. A method of mapping states of a multiple bit per cell memory deviceto binary data bits comprising: providing said multiple bit per cellmemory device with x multiple bit per cell memory cells, each with ystates; assigning a unique state to each of y^(x) possible states ofsaid multiple bit per cell memory device; mapping each assigned uniquestate to a unique binary state of n binary bits, where 2^(n)<y^(x) and nis an integer; and designating y^(x)−2^(n) additional states.
 28. Amethod of operating a multiple bit per cell memory device comprising:providing said multiple bit per cell memory device with x multiple bitper cell memory cells, each with y states; applying power to saidmultiple bit per cell memory device; running a self-test on each ofy^(x) possible states of said multiple bit per cell memory device toidentify z faulty states, wherein z≧0; assigning a unique state to eachof y^(x)−z working states of said multiple bit per cell memory device;mapping each assigned unique state to a unique binary state of n binarybits, where 2^(n)<y^(x) and n is an integer; and designatingy^(x)−z−2^(n) spare states as invalid data states.
 29. A method ofoperating a multiple bit per cell memory device comprising: providingsaid multiple bit per cell memory device with x multiple bit per cellmemory cells, each with y states; applying power to said multiple bitper cell memory device; running a self-test on each of y^(x) possiblestates of said multiple bit per cell memory device to identify z faultystates, wherein z≧0; assigning a unique state to each of y^(x)−z workingstates of said multiple bit per cell memory device; mapping eachassigned unique state to a unique binary state of n binary bits, where2^(n)<y^(x) and n is an integer; and designating y^(x)−z−2^(n) sparestates.
 30. A method of erasing data in a multiple bit per cell memorydevice comprising: providing said multiple bit per cell memory devicewith x multiple bit per cell memory cells, each with y states; assigninga unique state to each of y^(x) possible states of said multiple bit percell memory device; mapping each assigned unique state to a uniquebinary state of n binary bits, where 2^(n)<y^(x) and n is an integer;utilizing at least one of y^(x)−2^(n) spare states for indicating erasedmemory cells; reading each of said indicated erased memory cells todetermine whether it is erased or not erased; and erasing each of saidindicated erased memory cells only if it is not erased.